It has been known a display device which (i) includes a memory circuit in each pixel (hereinafter, referred to as a pixel memory) and (ii) is capable of displaying, by causing the pixel memory to store image data, a still image with low electric power consumption without necessity of image data being externally supplied consecutively (see, for example, Patent Literature 1). Note that, once image data is written into a pixel, it becomes no longer necessary (i) to charge or discharge a data signal line via which image data is supplied to the pixel and (ii) to externally transmit image data to a driver in the panel. As such, the breakdown of reduction in electric power consumption includes (i) a reduction in electric power consumed during the charge or discharge of the data signal line and (ii) a reduction in electric power consumed during the transmission of the image data.
An SRAM-type pixel memory and a DRAM-type pixel memory have been developed and employed as the pixel memory. According to the display device, since a pixel voltage is a digital signal, it becomes difficult for a crosstalk to occur. As such, the display device excels in display quality.
FIG. 25 is a view schematically illustrating a configuration of a display device disclosed in Patent Literature 1. FIG. 26 is a timing chart illustrating waveforms of respective signals supplied to the display device.
According to the display device, image data DR, DG, and DB are supplied to a display driver by a serial transmission while being included in serial data SI. A first flag D1, which indicates a polarity of a voltage of a common electrode (Vcom), is added to the serial data SI. The display driver extracts the first flag D1, in synchronization with a serial clock SCLK, from the serial data SI and then carries out display in accordance with the serial data SI. The display driver further supplies a voltage of a common electrode (Vcom) which has a polarity corresponding to the first flag D1 thus extracted.
With the configuration, a separate circuit for indicating a polarity of a common reverse is unnecessary. This makes it possible to generate, in a small-scale circuit, a timing signal for a common reverse.